1. Field of the Invention
The present invention generally relates to a method for generating layout pattern, and more particularly to a method for generating a layout pattern including FinFET layout pattern.
2. Description of the Prior Art
With the trend in the industry being towards scaling down the size of the metal oxide semiconductor field effect transistors (MOSFETs), three-dimensional or non-planar transistor technology, such as the fin field effect transistor (Fin FET) technology, has been developed to replace planar MOS transistors. Generally, patterned structures in a FinFET, such as fin structures, can be obtained by sidewall image transfer (SIT) through the following processes. First, a layout pattern is inputted into a computer system and is modified through suitable calculation. The modified layout is then defined in a mask and further transferred to a layer of sacrificial layer on a substrate through a photolithographic and an etching process. In this way, several sacrificial layers distributed with a same spacing and of a same width are formed on a substrate. Each of the sacrificial layers may be stripe-shaped. Subsequently, a deposition process and an etching process are carried out such that spacers are formed on the sidewalls of the patterned sacrificial layers. In a next step, sacrificial layers can be removed completely by performing an etching process. Through the etching process, the pattern defined by the spacers can be transferred into the underneath substrate so as to obtain required patterned structures, such as stripe patterned structures, in the substrate.
However, the layout pattern and the patterned structures produced from the above processes still have limitations. For example, due to limitations in the design in layouts of circuits and restrictions on the fabrication processes, the patterned sacrificial layers are often distributed with the same spacing and of the same width. This configuration causes the subsequently formed strip patterned structures to be only distributed with the same spacing or with an integral multiple of that spacing. This arrangement will restrict not only the available area on the substrate but also the design in the layout of the circuit, which reduces the applicability of the semiconductor devices.
Consequently, there is a need to provide an improved method for generating a layout pattern so as to overcome the above-mentioned drawbacks.